Variability is observed to proportionately increase with each succeeding generation of integrated circuit technology. Sources of such variability include, for example, manufacturing variations, device fatigue, environmental variations (such as temperature and power-supply voltage), and phase-locked loop (PLL) variations. In the presence of such variations, it is desirable to know the criticality of each signal propagation arc (e.g., timing arc) i.e., the probability of manufacturing an integrated circuit (e.g., chip) with a critical path going through a signal propagation arc of interest. Various applications can benefit from such a capability, including testing, timing reports, and circuit optimization.
Prior-art “deterministic” timing methods carry out the timing at a fixed process comer or “case.” Therefore, it can be difficult to predict probability distributions of circuit delay and criticalities of signal propagation arcs. Furthermore, in deterministic timing methods, the critical path is unique and is therefore the obvious target of improvement in optimization methods. In statistical timing, each path and each edge are observed to have some non-negative probability of being critical. It is desirable to predict these edge criticality probabilities in magnitude order to guide manual or automated optimization of integrated circuits.
Prior-art methods of predicting criticality probabilities suffer from such problems as inefficiency and inability to correctly take correlations into account. One way of computing criticalities is to apply Monte-Carlo simulation in a straightforward manner, by generating many random combinations of process parameters satisfying the given probability distributions, and then performing repeated deterministic timing analysis to detect the critical timing arcs for each individual combination of the process parameters. The fraction of circuits in which a particular edge is on the most critical path is the criticality probability of that edge. This approach, however, can be too computationally inefficient as it requires too many deterministic timing analyses.
Another prior-art method using parameterized statistical static analysis is described in U.S. patent application Ser. No. 10/666,470, entitled “System and Method for Probabilistic Criticality Prediction of Digital Circuits,” filed on Sep. 19, 2003, the entire contents of which are incorporated herein by reference. However, this approach implicitly assumes that “tightness probabilities” are independent probabilities. This assumption has disadvantages as the tightness probabilities can be strongly correlated due to both reconvergence of the signal propagation paths and dependence on common global sources of variation, leading to inaccurate prediction of criticality probabilities.
Accordingly, there is a need to overcome the above-noted problems.
The following United States Patent Applications relating to statistical timing analysis of digital circuits are commonly assigned to the assignee herein and are incorporated by reference herein in their entireties: U.S. patent application Ser. No. 10/665,092, entitled “System and Method for Incremental Statistical Timing Analysis of Digital Circuits,” filed on Sep. 18, 2003; U.S. patent application Ser. No. 10/666,353, entitled “System and Method for Statistical Timing Analysis of Digital Circuits,” filed on Sep. 19, 2003; and U.S. patent application Ser. No. 10/666,470, entitled “System and Method for Probabilistic Criticality Prediction of Digital Circuits,” filed on Sep. 19, 2003.